from 0, < 20210608-r0
HIGH8.2CVE-2023-45745Improper input validation in some Intel(R) TDX module software before version 1.5.05.46.698 may allow a privileged user to potentially enab… from 0, < 20240813-r0
from 0, < 20231114-r0
MEDIUM6.8intel-microcode - security update
from 0, < 20230214-r0
MEDIUM6.8Hardware allows activation of test or debug logic at runtime for some Intel(R) processors which may allow an unauthenticated user to potent…
from 0, < 20220207-r0
MEDIUM6.7Unauthorized error injection in Intel(R) SGX or Intel(R) TDX for some Intel(R) Xeon(R) Processors may allow a privileged user to potentiall…
from 0, < 20230808-r0
MEDIUM6.7Incorrect default permissions in some memory controller configurations for some Intel(R) Xeon(R) Processors when using Intel(R) Software Gu…
from 0, < 20230214-r0
MEDIUM6.5Protection mechanism failure of bus lock regulator for some Intel(R) Processors may allow an unauthenticated user to potentially enable den…
from 0, < 20240813-r0
MEDIUM6.5xen - security update
from 0, < 20240813-r0
MEDIUM6.5linux - security update
from 0, < 20230808-r0
MEDIUM6.5Domain-bypass transient execution vulnerability in some Intel Atom(R) Processors may allow an authenticated user to potentially enable info…
from 0, < 20210608-r0
MEDIUM6.5Improper isolation of shared resources in some Intel(R) Processors may allow an authenticated user to potentially enable information disclo…
from 0, < 20210608-r0
MEDIUM6.5intel-microcode - security update
from 0, < 20190918-r0
MEDIUM6.1intel-microcode - security update
from 0, < 20240813-r0
MEDIUM5.6intel-microcode - security update
from 0, < 20190514a-r0
MEDIUM5.6linux - security update
from 0, < 20190514a-r0
MEDIUM5.6Systems with microprocessors utilizing speculative execution and branch prediction may allow unauthorized disclosure of information to an a…
from 0, < 20190514a-r0
MEDIUM5.5Non-transparent sharing of return predictor targets between contexts in some Intel(R) Processors may allow an authorized user to potentiall…
from 0, < 20240813-r0
MEDIUM5.5Improper isolation of shared resources in some Intel(R) Processors may allow a privileged user to potentially enable information disclosure…
from 0, < 20220809-r0
MEDIUM5.5Processor optimization removal or modification of security-critical code for some Intel(R) Processors may allow an authenticated user to po…
from 0, < 20220510-r0
MEDIUM5.5Insufficient control flow management in some Intel(R) Processors may allow an authenticated user to potentially enable a denial of service…
from 0, < 20220207-r0
MEDIUM5.5Improper isolation of shared resources in some Intel(R) Processors may allow an authenticated user to potentially enable information disclo…
from 0, < 20201110-r0
MEDIUM5.5Insufficient access control in the Linux kernel driver for some Intel(R) Processors may allow an authenticated user to potentially enable i…
from 0, < 20201110-r0
MEDIUM5.5Cleanup errors in some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.
from 0, < 20200609-r0
MEDIUM5.3Incorrect calculation in microcode keying mechanism for some Intel(R) Xeon(R) D Processors with Intel(R) SGX may allow a privileged user to…
from 0, < 20240813-r0
MEDIUM4.7Sequence of processor instructions leads to unexpected behavior in Intel(R) Core(TM) Ultra Processors may allow an authenticated user to po…
from 0, < 20240813-r0
MEDIUM4.4Improper access control in some 3rd Generation Intel(R) Xeon(R) Scalable processors may allow a privileged user to potentially enable infor…
from 0, < 20230808-r0
MEDIUM4.4Improper isolation of shared resources in some Intel(R) Processors when using Intel(R) Software Guard Extensions may allow a privileged use…
from 0, < 20230214-r0
LOW2.8Hardware logic contains race conditions in some Intel(R) Processors may allow an authenticated user to potentially enable partial informati…
from 0, < 20240813-r0
—Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution for some Intel(R)…
from 0, < 20260512-r0
—Improper handling of values in the microcode flow for some Intel(R) Processor Family may allow an escalation of privilege.
from 0, < 20260210-r0
—Improperly implemented security check for standard in the DDRIO configuration for some Intel(R) Xeon(R) 6 Processors when using Intel(R) SG…
from 0, < 20250812-r0
—Out-of-bounds write in the memory subsystem for some Intel(R) Xeon(R) 6 processors when using Intel(R) SGX or Intel(R) TDX may allow a priv…
from 0, < 20250812-r0
—Insufficient control flow management in the Alias Checking Trusted Module (ACTM) firmware for some Intel(R) Xeon(R) processors may allow a…
from 0, < 20250812-r0
—Improper handling of overlap between protected memory ranges for some Intel(R) Xeon(R) 6 processor with Intel(R) TDX may allow a privileged…
from 0, < 20250812-r0
—Sequence of processor instructions leads to unexpected behavior for some Intel(R) Xeon(R) 6 Scalable processors may allow an authenticated…
from 0, < 20250812-r0
—Insufficient granularity of access control in the OOB-MSM for some Intel(R) Xeon(R) 6 Scalable processors may allow a privileged user to po…
from 0, < 20250812-r0
—Missing reference to active allocated resource for some Intel(R) Xeon(R) processors may allow an authenticated user to potentially enable d…
from 0, < 20250812-r0
—Improper Isolation or Compartmentalization in the stream cache mechanism for some Intel(R) Processors may allow an authenticated user to po…
from 0, < 20250812-r0
—intel-microcode - security update
from 0, < 20250812-r0
—Incorrect initialization of resource in the branch prediction unit for some Intel(R) Core™ Ultra Processors may allow an authenticated user…
from 0, < 20250512-r0
—Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution for some Intel(R)…
from 0, < 20250512-r0
—Insufficient resource pool in the core management mechanism for some Intel(R) Processors may allow an authenticated user to potentially ena…
from 0, < 20250512-r0
—Uncaught exception in the core management mechanism for some Intel(R) Processors may allow an authenticated user to potentially enable deni…
from 0, < 20250512-r0
—Incorrect behavior order for some Intel(R) Core™ Ultra Processors may allow an unauthenticated user to potentially enable information discl…
from 0, < 20250512-r0
—Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution in the indirect b…
from 0, < 20250512-r0
—Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution for some Intel At…
from 0, < 20250512-r0
—xen - security update
from 0, < 20250512-r0
—Improper handling of physical or environmental conditions in some Intel(R) Processors may allow an authenticated user to enable denial of s…
from 0, < 20250211-r0
—Sequence of processor instructions leads to unexpected behavior in the Intel(R) DSA V1.0 for some Intel(R) Xeon(R) Processors may allow an…
from 0, < 20250211-r0
—Improper access control in the EDECCSSA user leaf function for some Intel(R) Processors with Intel(R) SGX may allow an authenticated user t…
from 0, < 20250211-r0
—Improper Finite State Machines (FSMs) in Hardware Logic for some Intel(R) Processors may allow privileged user to potentially enable denial…
from 0, < 20250211-r0
—Improper input validation in UEFI firmware for some Intel(R) processors may allow a privileged user to potentially enable escalation of pri…
from 0, < 20250211-r0
—Improper conditions check in some Intel(R) Xeon(R) processor memory controller configurations when using Intel(R) SGX may allow a privilege…
from 0, < 20241112-r0
—Improper finite state machines (FSMs) in the hardware logic in some 4th and 5th Generation Intel(R) Xeon(R) Processors may allow an authori…
from 0, < 20241112-r0
—Improper finite state machines (FSMs) in hardware logic in some Intel(R) Processors may allow an privileged user to potentially enable a de…
from 0, < 20240910-r0
—intel-microcode - security update
from 0, < 20240910-r0
—Mirrored regions with different values in 3rd Generation Intel(R) Xeon(R) Scalable Processors may allow a privileged user to potentially en…
from 0, < 20240813-r0
—Protection mechanism failure in some 3rd, 4th, and 5th Generation Intel(R) Xeon(R) Processors may allow a privileged user to potentially en…
from 0, < 20240813-r0
—Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a priv…
from 0, < 20240813-r0
—Improper isolation in some Intel(R) Processors stream cache mechanism may allow an authenticated user to potentially enable escalation of p…
from 0, < 20240813-r0
—Improper isolation in the Intel(R) Core(TM) Ultra Processor stream cache mechanism may allow an authenticated user to potentially enable es…
from 0, < 20240813-r0